Memories, such as static random access memories (SRAMs), dynamic random access memories (DRAMs) and nonvolatile memories (NVM) typically comprise a plurality of memory cells that are capable of storing a charge representing a data bit. These memory cells are often arranged in an array of intersecting rows and columns. Conventionally, the lines running adjacent to each row of memory cells are called word lines, and the lines running adjacent to each column of memory cells are called bit lines. By selectively applying activation voltages to these word lines and bit lines, the memory cells can be accessed. In general, word lines activate memory cells and bit lines provide data to or retrieve data from the activated memory cells.
A read or write function to a memory cell is performed by applying an activation voltage to the word line by a word line driver. When an activation voltage is applied to the word line, specific circuitry in the memory cell is activated that enables a bit line to write data to or retrieve data from the activated memory cell. Typically, a word line driver applies a positive voltage level to the word line to activate the word line.
FIG. 1 shows a high level diagram of a conventional word line address scan system 100. A conventional address scan may comprise an address decoder 104 for receiving an address, a memory array 108 for storing data corresponding to the address and a compare data module 109 for comparing the data read from the memory array 108 which is a function of the input address with the expected data.
Conventional word line address scan systems have several disadvantages. For example, the voltage levels between the memory array and those of the address decoder may vary significantly depending on the memory technology. This is especially true for certain non-volatile memories like Flash which use transistors with floating gates that are driven by higher voltages. Often additional circuitry is necessary to up-shift the voltages to drive the word line to a higher voltage. Thus, the testing of certain memory addressing and word line driving circuitries may be difficult due to the voltage mismatch involved.
Additionally, conventional word line address scan systems do not test, either individually or in combination, whether a word line of memory cells is correctly selected, whether a word line voltage rises to a target voltage within a specified short time frame, and that no other word line is selected at the same time. It would be desirable to have a word line address scan system that allows testing of only one or a combination of two or three of these testing parameters.
A further disadvantage of conventional word line address scan systems is the lack of fast “disaster checks” for the above listed testing parameters which can be implemented at low cost and high speed and may also be used permanently during system operation without disturbing the current system. This is especially important for safety applications. For example, it would be desirable to have a word line address scan that tests whether a single word line is selected, and not two or more, in a safety application for quick checks without the need to involve the whole address encoding and decoding circuitry.
Conventional word line address scan systems are inadequate to address these disadvantages without significantly increasing costs and complexity. Therefore, there exists a need for a word line address scan system and method which provides several tests of a word line addressing circuitry of a flash memory including whether only one word line is selected, whether the correct word line is selected, and whether the word line voltage rises within a given time frame. Moreover, there is a need for a system that allows only one or a combination of these tests, especially as a disaster check during safety applications.